1. Technical Field
The present invention relates to a data converter, and more particularly to a multi-bid data converter using data weight averaging.
2. Discussion of the Related Art
In a mixed-mode signal processing system for processing an analog signal and a digital signal, a data converter is used. The data converter includes an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). Various data converters having high resolution have been developed.
In both the ADC and the DAC, a sampling technique is used. Among various sampling techniques, Nyquist sampling and oversampling techniques are widely used.
The Nyquist sampling technique uses precise unit elements and is vulnerable to noise and signal interference. Therefore, high resolution is difficult to achieve in a data converter.
A data converter using the oversampling technique samples with much higher (for example, 64 times or 128 times) frequency than the frequency of a signal band. Configuration of the data converter using the oversampling technique is relatively complex and the data converter using the oversampling technique uses an internal circuit having high-speed operation. However, the data converter using the oversampling technique needs comparatively less precise unit elements and is not as vulnerable to noise and signal interference as data converters using the Nyquist sampling technique. Therefore, a higher resolution in the data converter can be achieved using the oversampling technique.
Among several oversampling data converters, a delta-sigma data converter using a delta-sigma modulator may generate high signal-to-noise ratio (SNR) because the delta-sigma data converter performs noise shaping by moving noise energy in a signal band to a high frequency band. Therefore, the delta-sigma data converter is widely used for signal processing in a low frequency and a narrow band such as an audio signal that requires a high resolution and a high SNR.
Among delta-sigma data converters, a delta-sigma data converter using a 1-bit delta signal modulator and an internal 1-bit DAC performs quantization in two steps. Therefore, linearity of the conversion process can be achieved. However, the 1-bit delta signal modulator uses a high-level modulator configuration so as to achieve a high-resolution. The high-level modulator has several problems such as large size, high power consumption and low stability due to generation of an oscillation.
When a multi-bit delta-sigma modulator and an internal multi-bit DAC are used, stability of a whole system can be increased and a high SNR can be achieved with a relatively low oversampling ratio because a low-level delta-sigma modulator is used. However, a data converter using the multi-bit delta-sigma modulator and the internal multi-bit DAC may have noise generated due to mismatched current sources in the internal multi-bit DAC.
FIG. 1 is a block diagram illustrating a general multi-bit DAC.
A 3-bit DAC including eight numbers of current sources is illustrated in FIG. 1. Each of the current sources is designed to generate the same current with respect to one another. However, fluctuations between the respective current sources, that is, a mismatching is caused due to variances of the manufacturing process.
In FIG. 1, current sources having mismatching of −3% through 1% are illustrated.
The multi-bit DAC connects or separates eight switches (that is, unit elements), respectively, based on an input data. When the same data is inputted, the same error is generated because the same switches corresponding to the same input data are connected.
FIG. 2A is a diagram illustrating mismatching linearity noise that is generated when a data weight averaging (DWA) technique is not used in the multi-bit DAC of FIG. 1.
Referring to FIG. 2A, when an input data is 1, only switch SW0 is connected and 1% error is generated. When the input data is 2, switches SW0 and SW1 are connected and 1%+1%, that is, 2% error is generated. When the input data is 3, switches SW0, SW1 and SW2 are connected and 1%+1%+(−3%), that is, −1% error is generated. The same mismatching is generated when the same data is inputted because each current source is predetermined to be selected according to the input data. Therefore, errors according to repeated data are not dispersed to form a low bandwidth, and thus the mismatching error appears within an analog signal band.
A technique for dynamically allocating each of the unit elements has been developed, called dynamic element matching (DEM), to resolve mismatched elements. When unit elements such as current sources are selected randomly, errors are also generated randomly, and thus the noise due to the random errors may be converted to white noise. However, generating a control signal for randomly selecting unit elements uses a relatively complex algorithm and additional corrections. Therefore, methods for spreading the mismatching noise into much wider band than a signal band so as to sufficiently lower a noise floor even though errors are not completely random have been suggested. Among the methods, a DWA method for sequentially selecting unit elements corresponding to a digital input data is widely used.
FIG. 2B is a diagram illustrating mismatching linearity noise that is generated when a DWA technique is used in the multi-bit DAC of FIG. 1.
When input data are 1, 1, and 1, switches SW0, SW1 and SW2 are connected in sequential order and 1%, 1% and −3% errors are generated, respectively. When the input data are 2, 2 and 2, two switches SW3 and SW4, two switches SW5 and SW6 and then two switches SW7 and SW0 are connected in sequential order and 0%, 0%, and 2% errors are generated. When the input data is changed to 3, three switches SW1, SW2 and SW3, three switches SW4, SW5 and SW6, and three switches SW7, SW0 and SW1 are connected in sequential order and −4%, 2% and 3% errors are generated. An error change according to the data is dispersed and noise due to a mismatching is moved to a high band because current sources are sequentially selected. However, when specific data are repeatedly or periodically inputted, use of the conventional DEM generates a tone in the signal band. When the specific data are repeatedly inputted, specific errors are repeatedly generated and the errors cannot be averaged.
FIG. 3 is a diagram illustrating a tone generation when a conventional DWA is adopted. Referring to FIG. 3, specific data ‘3, 4, 1, 3, 4, 1’, is periodically inputted. Then, three unit elements SW0 through SW2, four unit elements SW3 through SW6, and one unit element SW7 are connected in sequential order and mismatching errors are also repeatedly generated. Because noise due to the mismatching errors is generated in a signal band, SNR may be decreased.
In case of a multi-bit DAC having a small bit number such as an audio signal processing system, the possibility of repeated or periodical specific data is high because data types inputted to the multi-bit DAC are simple and the noise due to repeated input data may be in the audible range.